medium5.9
CVE-2020-0574
Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege a…
Impact
Improper configuration in block design for Intel(R) MAX(R) 10 FPGA all versions may allow an authenticated user to potentially enable escalation of privilege and information disclosure via physical access.
Affected products
| Vendor | Product | Affected versions |
|---|---|---|
| Intel | Max 10 Fpga Firmware | All versions |