high7.9
CVE-2025-0647
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the…
Impact
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
Affected products
| Vendor | Product | Affected versions |
|---|---|---|
| Arm | C1-Ultra Firmware | All versions |
| Arm | C1-Premium Firmware | All versions |
| Arm | Cortex-A710 Firmware | All versions |
| Arm | Cortex-X2 Firmware | All versions |
| Arm | Cortex-X3 Firmware | All versions |
| Arm | Cortex-X4 Firmware | All versions |
| Arm | Cortex-X925 Firmware | All versions |
| Arm | Neoverse-V2 Firmware | All versions |
| Arm | Neoverse-V3 Firmware | All versions |
| Arm | Neoverse-V3ae Firmware | All versions |
| Arm | Neoverse-N2 Firmware | All versions |